1. Field of Invention
The present invention relates to a method of manufacturing semiconductor devices. More particularly, the present invention relates to a method of manufacturing the metallic capacitor electrodes of a mixed mode semiconductor device.
2. Description of Related Art
In general, the analog portion of mixed mode logic circuit uses a pair of polysilicon layers as the electrodes of a capacitor. However, polysilicon electrodes have a number defects including the formation of depletion layers. Depletion layers in the polysilicon electrode will result in the dependency of charging/discharging operations of a capacitor on the number of manufacturing defects. Moreover, the process of fabricating polysilicon electrodes is relatively complicated.
In particular, heat treatment, etching and capacitor efficiency are difficult to control. Furthermore, the resistance of a polysilicon electrode is quite high. Consequently, capacitors having metallic electrodes are gradually replacing the conventional polysilicon electrodes. However, there are several processing problems in the fabrication of metallic electrodes including the etching of metallic layer and the damaging effect of etching on the peripheral dielectric layer.
FIGS. 1A through 1D are cross-sectional views showing the progression of manufacturing steps in forming the metallic electrodes of a capacitor in a mixed mode semiconductor device according to a conventional method. First, as shown in FIG. 1A, a substrate 10 is provided, and then a sputtering method or chemical vapor deposition method is used to deposit a metallic layer. Next, conventional photolithographic and etching processes are used to pattern the metallic layer to form metallic layers 12 and 14. The metallic layer 12 serves as the lower electrode of the capacitor, whereas the metallic layer 14 serves as an interconnect wire.
Next, as shown in FIG. 1B, a chemical vapor deposition method is used to form an oxide layer 16 over the substrate 10 and the metallic layers 12 and 14. Thereafter, a sputtering method or a chemical vapor deposition method is used to form a metallic layer 18 over the oxide layer 16.
Next, as shown in FIG. 1C, conventional photolithographic and etching processes are used to pattern the metallic layer 18 and the oxide layer 16, thereby forming a metallic layer 20 and a dielectric layer 22, respectively. The metallic layer 20 serves as the upper electrode of the capacitor and is above the metallic layer 12. In the conventional technique, the metallic layer 20 does not cover the metallic layer 12 completely so that a portion of the metallic layer 12 is exposed.
In the process of patterning the metallic layer 18 and the oxide layer 16 to form the metallic layer 20 and the dielectric layer 22, etching must stop precisely at the metallic layer 12. However, the metallic layer 12 is flanked by a thick metallic layer 18. Since the metallic layer 12 and the metallic layer 18 are made from metallic material, the metallic layer 12 may be over-etched thus damaging the region 21 above the metallic layer 12. In addition, a portion of the dielectric layer 22 may also be damaged leading to a degeneration of its insulating effects.
Next, as shown in FIG. 1D, a low-pressure chemical vapor deposition method is used to form a dielectric layer 23 over the entire semiconductor structure including the metallic layer 14, the metallic layer 20 and the exposed metallic layer 12. Subsequently, conventional photolithographic and etching processes are again used to form dielectric openings 24, 26 and 28. The openings 24, 26 and 28 expose the metallic layer 14, the metallic layer 20 and the metallic layer 12, respectively. After that, a sputtering method or a chemical vapor deposition method is again used to deposit a layer of metallic material into the openings 24, 26 and 28, thereby forming metal plugs 30, 32 and 34, respectively. The metal plugs 30, 32 and 34 form electrical contact with metallic layers 14, 20 and 12, respectively. Finally, other processing operations necessary for forming a complete semiconductor device are carried out.
However, the aforementioned technique of forming metal electrodes in a capacitor has other defects too. Because the step height between semiconductor devices is high, subsequent processing operations are difficult to carry out. Since difference in depth between dielectric openings varies considerably due to a great different in their step height, judging when to stop the etching operation becomes difficult.
In light of the foregoing, there is a need to provide an improved method of forming the metallic electrodes of a capacitor.